LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE WORK.chooser;

--TESTBENCH DO CHOOSER

ENTITY tb_chooser IS
END tb_chooser;

ARCHITECTURE logic OF tb_chooser IS

COMPONENT chooser
    PORT(ic: IN STD_LOGIC_VECTOR(11 DOWNTO 0);
		  chosen: OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;

SIGNAL ic_in: STD_LOGIC_VECTOR(11 DOWNTO 0) := "000000000000";
SIGNAL s_chosen: STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN
    decisor: chooser
    PORT MAP(ic=>ic_in, chosen=>s_chosen);
    PROCESS
        TYPE pattern_record IS RECORD
            vi_ic: STD_LOGIC_VECTOR(11 DOWNTO 0);
            vo_chosen: STD_LOGIC_VECTOR(1 DOWNTO 0);
        END RECORD;
        TYPE pattern_tests IS ARRAY (NATURAL RANGE <>) OF pattern_record;
            CONSTANT patterns : pattern_tests :=
            (
                ("000000000000", "00"),
                ("100000000000", "01"),
                ("110000000000", "10"),
                ("010000000000", "01"),
                ("011000000000", "10"),
                ("001000000000", "01"),
                ("001100000000", "10"),
                ("000100000000", "01"),
                ("000110000000", "10"),
                ("000010000000", "01"),
                ("000011000000", "10"),
                ("000001000000", "01"),
                ("000001100000", "10"),
                ("000000100000", "01"),
                ("000000110000", "10"),
                ("000000010000", "01"),
                ("000000011000", "10"),
                ("000000001000", "01"),
                ("000000001100", "10"),
                ("000000000100", "01"),
                ("000000000110", "10"),
                ("000000000010", "01"),
                ("000000000011", "10"),
                ("000000000001", "01"),
                ("101010101010", "10"),
                ("010101010101", "10")
            );
    BEGIN
        FOR i IN patterns'RANGE LOOP
				ic_in <=  patterns(i).vi_ic;
            WAIT FOR 100 ps;
				ASSERT s_chosen = patterns(i).vo_chosen REPORT "VALOR DE CHOSEN ERRADO" SEVERITY error;
        END LOOP;
        ASSERT false REPORT "END." SEVERITY note;
        WAIT;
    END PROCESS;
END logic;
